Semiconductor structure

ABSTRACT

The present invention discloses a semiconductor structure comprising a semiconductor substrate having a U-shape trench, a U-shape gate dielectric layer on the U-shape trench, a U-shape gate region on the U-shape gate dielectric layer, a conducting matter in the U-shape gate region, and a cover dielectric layer on the conducting matter. The semiconductor structure may have a minimized size and when recess channels are formed thereby, the integration is accordingly improved without suffering from the short channel effect.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a structure of a semiconductor device,and particularly to a structure of a buried word line.

2. Description of the Prior Art

As electronic products are becoming lighter, thinner, shorter, andsmaller, dynamic random access memory (DRAM) geometries are being scaleddown to match the trends of high integration and high density. DRAMcomposed of a lot of memory cells is one of the most popular volatilememory devices. Each memory cell of DRAM comprises a MOS(metal-oxide-semiconductor) transistor and at least a capacitor stackedeach other in a series connection. By using word lines and bit lines,DRAM can be read and programmed.

In order to miniaturize DRAM, gate channel length is shortened, but theshort channel effect becomes an obstacle to the improvement of theintegration of the semiconductor device. Methods of avoiding the shortchannel effect had been proposed, for example, decreasing the thicknessof the gate oxide layer, increasing dopant concentration, and the like.However, theses methods may encounter some problems, such as low elementreliability and slow data transfer rates, and are unsuitable to beactually used.

In order to solve these problems, a hole type recess channel MOStransistor has been developed and gradually adopted to increase theintegration. In comparison with a conventional horizontal MOStransistor, the hole type recess channel MOS transistor includes thegate and the source/drain formed in an etched trench of a semiconductorsubstrate, and furthermore, the gate channel region is disposed at thebottom portion of the trench, thereby to reduce the horizontal area ofthe MOS transistor for improving the device integration.

FIG. 1 illustrates a schematically cross-sectional view of a recesschannel MOS transistor device having a gate structure and a word linestructure thereabove, which is constructed in a semiconductor substrate10. The MOS transistor includes a gate oxide layer 12, a polysiliconlayer 14, a doped polysilicon layer 16, an inner spacer 18, apolysilicon layer 20, a tungsten metal layer 22, a silicon nitride layer24, and spacers 26. The tungsten metal layer 22 serving as a word lineis disposed above the surface of the semiconductor substrate 10.

To improve the integration of a semiconductor device is constantly asubject to be researched and developed, and, therefore, there is still aneed for a novel MOS transistor device structure.

SUMMARY OF THE INVENTION

One object of the present invention is to provide a structure of aburied word line, which has a film stack structure. Each film may bevery thin, and accordingly the integration of the semiconductor devicecan be improved.

The semiconductor structure according to the present invention comprisesa semiconductor substrate having a U-shaped trench in the semiconductorsubstrate; a U-shaped gate dielectric layer formed on a surface of theU-shaped trench; a U-shaped gate region formed on a top surface of theU-shaped gate dielectric layer; a conducting matter formed in theU-shaped trench and enclosed by the U-shaped gate region, wherein theconducting matter is electrically connected to the U-shaped gate region;and a cover dielectric layer formed on top of the U-shaped trench tocover the U-shaped gate region and the conducting matter.

The semiconductor structure according to the present invention is a filmstack structure, in which, a buried word line and a recess channel isformed in the semiconductor substrate. Since each film of the film stackstructure can be very thin, the integration of the semiconductor devicecan be improved. Furthermore, due to the design of recess channel, theshort channel effect can be avoided.

These and other objectives of the present invention will no doubt becomeobvious to those of ordinary skill in the art after reading thefollowing detailed description of the preferred embodiment that isillustrated in the various figures and drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 illustrates a schematically cross-sectional view of aconventional recess channel MOS transistor device having a gatestructure and a word line structure above the gate structure;

FIGS. 2 and 3 illustrate schematically cross-sectional views of someembodiments of the semiconductor structure according to the presentinvention; and

FIGS. 4 and 5 illustrate schematically partially cross-sectional viewsand partially perspective views of some embodiments of the semiconductorstructure according to the present invention.

DETAILED DESCRIPTION

FIG. 2 illustrates a schematically cross-sectional view of an embodimentof the present invention, which may be utilized in an EUD typetransistor. The semiconductor structure as shown in FIG. 2 comprises asemiconductor substrate 50 and a film stack structure of a U-shape gatedielectric layer 52, a U-shape gate region 54, a conducting layer 56,and a cover dielectric layer 58.

The semiconductor substrate 50 has a U-shaped trench therein. TheU-shape gate dielectric layer 52 is disposed on the surface of theU-shape trench of the semiconductor substrate 50 and may be for examplea silicon oxide compound layer formed by the oxidation of the silicon atthe surface of the semiconductor substrate. It has to be mentioned herethat the surface of the U-shape trench of the semiconductor substrate 50means for the inner surface of the U-shape trench or the outer surfaceof the U-shape trench.

The U-shape gate region 54 is disposed in the U-shape trench formed inthe U-shape gate dielectric layer 52. The gate region 54 may bedeposited into the trench by deposition and then etched back to form arecess for subsequent formation of the conducting layer therein. Thegate region 54 may comprise, for example, polysilicon.

The conducting layer 56 is disposed in the recess of the U-shape gateregion 54 to serve as a word line and may comprise, for example, oneselected from the group consisting of tungsten, nickel, copper, cobalt,a combination thereof, and a silicide thereof or a material of lowresistance.

A cover dielectric layer 58 covers the top of the conducting layer 56and the top of the U-shape gate region 54. The cover dielectric layer 58and the gate dielectric layer 52 together separate the conducting layer56 and the U-shape gate region 54 from the semiconductor substrate 50.The cover dielectric layer may include dielectric material such assilicon nitride, silicon oxide, and the like. The height of the bottomof the cover dielectric layer 58 is substantially lower than the heightof the top 60 of the semiconductor substrate 50. In such structure, thesemiconductor structure according to the present invention is entirelyburied in the semiconductor substrate, such that the part of thesemiconductor substrate 50 surrounding the U-shape gate dielectric layer52 forms a gate channel.

Furthermore, an adhesive layer 62 may be optionally disposed between theU-shape gate region 54 and the conducting layer 56, as shown in FIG. 3.The adhesive layer 62 is also in a U-shape because it is between theU-shape gate region and the conducting layer. The adhesive layer 62 maycomprise one selected from the group consisting of titanium, tantalum,an alloy thereof, and a nitride thereof, for example, Ti, Ta, TiN, TaN,TiTa alloy, and the like, or a material of low resistance. The adhesivelayer improves the adhesion of the conducting layer to the gate regionand also plays a role as a barrier layer to inhibit the diffusion of theingredients of the conducting layer into the gate region to affect theelectric properties.

Furthermore, the semiconductor structure according to the presentinvention may have other modified aspects. For example, referring toFIG. 4 showing a schematically partially cross-sectional view andpartially perspective view of a semiconductor structure according to thepresent invention, the bottom portions of the U-shape trench of thesemiconductor substrate, the U-shape gate dielectric layer 52, theU-shape gate region 54, and the conducting layer 56 together may have anindent, such that the semiconductor substrate has a corresponding finstructure. Alternatively, the semiconductor structure may further havean adhesive layer, as shown in FIG. 5. The bottom portions of theU-shape trench of the semiconductor substrate, the U-shape gatedielectric layer 52, the U-shape gate region 54, the adhesive layer 62,and the conducting layer 56 may together have an indent, such that thesemiconductor substrate has a corresponding fin structure. Suchstructure may be utilized in a fin transistor.

Those skilled in the art will readily observe that numerousmodifications and alterations of the device and method may be made whileretaining the teachings of the invention.

1. A semiconductor structure comprising: a semiconductor substratehaving a U-shaped trench in the semiconductor substrate; a U-shaped gatedielectric layer formed on a surface of the U-shaped trench; a U-shapedgate region formed on a top surface of the U-shaped gate dielectriclayer; a conducting matter formed in the U-shaped trench and enclosed bythe U-shaped gate region, wherein the conducting matter is electricallyconnected to the U-shaped gate region; and a cover dielectric layerformed on top of the U-shaped trench to cover the U-shaped gate regionand the conducting matter.
 2. The semiconductor structure of claim 1,wherein the conducting matter is served as a word line.
 3. Thesemiconductor structure of claim 1, wherein the conducting mattercomprises a material selected from the group consisting of tungsten,nickel, copper, cobalt, a combination thereof, and a silicide thereof.4. The semiconductor structure of claim 1 further comprising a U-shapedadhesive layer formed between the U-shaped gate region and theconducting matter.
 5. The semiconductor structure of claim 4, whereinthe adhesive layer comprises a material selected from the groupconsisting of titanium, tantalum, an alloy thereof, and a nitridethereof.
 6. The semiconductor structure of claim 4, wherein the coverdielectric layer covers the adhesive layer on top of the U-shapedtrench.